The present invention generally relates to the field of integrated circuits. More particularly, the present invention relates to providing capacitance to integrated circuits from gate array structures formed in a semiconductor substrate.
Today, integrated circuits (“ICs”) may contain millions of transistors on a single chip, with many critical circuit features having measurements in the deep sub-micron range. ICs are fabricated layer by layer on a semiconductor substrate. Using techniques known in the art of semiconductor fabrication, metal-oxide-semiconductor (“MOS”) transistors, bipolar transistors, diodes and other devices are fabricated and combined to form an IC on a substrate. Typically, portions of some of the devices and some interconnections are frequently formed using one or more levels of polysilicon. For example, a MOS transistor gate electrode and a resistor may be fabricated from a layer of polysilicon.
The IC layers are fabricated through a sequence of pattern definition steps that are mixed with other process steps such as oxidation, etching, doping, and material deposition. One or more metal layers are then deposited on top of the base layers to form conductive segments that interconnect IC components. Formation of the metallization layers over the substrate facilitates interconnection of the transistors to form more complex devices such as NAND gates, inverters, and the like. These metallization layers may also be used to provide power supply ground (VSS) and power supply voltage (VDD) to such IC devices.
The metallization layers utilize lines, contacts, and vias to interconnect the transistors in each of the cells as well as to interconnect the cells to form the integrated circuit, such as a processor, state machine, or memory. Lines in adjacent vertical layers often run perpendicular to one another, the adjacent vertical layers separated by a non-conductive passivation layer such as, e.g., silicon oxide. The silicon oxide is etched to form the vias, which interconnect the lines of various metallization layers in accordance with the circuit design. Inputs and outputs of the integrated circuit are brought to a surface with vias to bond the circuits with pins of a chip package. The chip package typically includes an epoxy or ceramic that encloses the integrated circuit to protect the circuit from damage and pins to facilitate a connection between the inputs and outputs of the integrated circuit and, e.g., a printed circuit board.
As stated above, the finished product IC may contain millions of transistors. Many of these transistors may operate with rapid switching rates. The operation of low-power, high-speed integrated circuits may be affected by these rapid switching rates. The extremely rapid switching rates of the transistor and other discrete components that make up integrated circuits typically cause current transients in the power buses of the integrated circuits. These current transients may last for several nanoseconds. Unfortunately, the power supply for the circuit may require much more time, such as several microseconds, to compensate for the transient currents drawn from the power bus by the discrete components. As a consequence, these transient currents from the power bus cause noise in power supply rails. Low gate threshold voltages of the various discrete components in ICs require the power supply bus to deliver a stable voltage, with minimum voltage level variations. Consequently, power supply bus stability, in terms of current response and voltage level fluctuation, is a significant issue in the design of an integrated circuit.
The conventional approach for stabilizing the power supply bus is to insert decoupling capacitors between the power supply bus and the IC circuit elements. Decoupling capacitors placed near power consuming circuits tend to stabilize, or smooth out, voltage variations by utilizing the charge stored within the decoupling capacitor. The stored charge may be thought of as a local power supply, providing power during the times that the discrete components switch rapidly. The net result being that the decoupling capacitors help mitigate the effects of voltage noise induced onto the system power supply bus.
Generally, IC designers may incorporate decoupling capacitance directly on the IC by only a few means, such as using thin oxide capacitance, metal-to-metal capacitance, and junction capacitance. While thin oxide capacitance, such as that associated with device gate oxide, offers the highest capacitance per unit area, it also has higher gate leakage and tends to lower IC fabrication yield due to gate oxide shorts than the other capacitance options.
Today, gate oxide thickness of ICs is merely a few layers of atoms and is approaching fundamental limits. For example, in a typical complimentary metal-oxide-semiconductor (CMOS) device the gate oxide thickness is often less than two nanometers. Consequently, such a small thickness makes the device susceptible to the effects of gate leakage current from other circuit components coupled with the device. One example is gate tunneling leakage current generated by one or more decoupling capacitors that couple the device to the power bus. Another example is a gate oxide defect causing a short between two plates. Small holes, or other defects in the oxide, often result in gate oxide leakage currents.
Typically, thin oxide structures used to create decoupling capacitance are field effect transistor (fet) based devices with wide device widths and relatively long channels. These structures are generally interspersed with the logic gates of the IC circuit design. Vacant regions of an IC may also be populated with gate array back fill cells, to allow designers to satisfy pattern density requirements and allow engineers to incorporate design changes. Unfortunately, the precise need for decoupling capacitance is not known until the IC circuit design has been placed and routed. Decoupling capacitance needs may disrupt the design process, requiring designers and engineers to rearrange the initial circuit placement to accommodate insertion of the decoupling capacitance structures.
Using deep sub-micron technology to design ICs, combined with the strict need for minimizing leakage currents and the need to have adequate amounts of decoupling capacitance, presents circuit designers with numerous design problems. What is needed is a new apparatus for creating decoupling capacitance using gate array cells while minimizing yield losses due to gate oxide defects, leakage current, and placement disruption.